The Cortex-A9 is the highest-performing ARM processor a decade ago and offers the rich capabilities of the widely supported ARMv7 architecture. The Cortex-A9 processor is designed to create state-of-the-art, highly-efficient, variable-length dynamically-variable, multi-instruction execution superscalar architectures, providing an 8-stage pipeline processor that executes out-of-order guesses, with a wide range of The features needed for cutting-edge products in consumer, network, enterprise and mobile applications, it can provide unprecedented high performance and energy efficiency.
ARM processor introductionARM (Advanced RISC Machines) A ​​32-bit Reduced Instruction Set (RISC) processor architecture, ARM processors are widely used in many embedded system designs. The ARM processor features fixed instruction length, high execution efficiency, and low cost.
ARM processing features1, small size, low power consumption, low cost, high performance;
2, support Thumb (16 bit) / ARM (32 bit) dual instruction set, can be well compatible with 8-bit / 16-bit devices;
3, the use of a large number of registers, instruction execution faster;
Most data operations are done in registers.
5, addressing method is flexible and simple, high efficiency;
6, the command length is fixed.
The Cortex-A9 microarchitecture can be used on both scalable multicore processors (Cortex-A9 MPCoreTM multicore processors) and on more traditional processors (Cortex-A9 single core processors).
The Cortex-A9 microarchitecture offers two options: the scalable Cortex-A9 MPCoreTM multi-core processor and the more traditional Cortex-A9 single-core processor. The scalable multi-core processor and single-core processor support the configuration of 16-, 32-, or 64-KB 4-way set-associative L1 caches with unmatched flexibility to meet specific application and market requirements.
The Cortex-A9 processor boasts second-to-none performance and power efficiency. It is an ideal solution for low-power, cost-sensitive, single-core processor-based devices that require high performance. Existing ARM11TM processor-level designs not only require increased performance and power efficiency without increasing silicon cost and power consumption, but also require maintaining a highly compatible software environment. Therefore, the Cortex-A9 processor uses a convenient Integrated IP delivery provides an ideal upgrade path for existing ARM11TM.
The Cortex-A9 single-core processor provides two low-latency Harvard 64-bit AMBA 3AXITM Master interfaces for independent instruction and data transfers, maintaining four double-word writes every five processor cycles while copying data through the memory cache.
Cortex-A9 multi-core processorThe Cortex-A9 multi-core processor integrates the highly successful ARM MPCore technology and more enhancements to simplify the multi-core solution and extend its application range. The Cortex-A9 MPCore processor delivers unprecedented, scalable maximum performance while also supporting flexible design and new features to further reduce and control processor and system level power consumption. With the directional implementation of the Cortex-A9 MPCore processor, the maximum performance of mobile devices can also be continuously improved on the basis of the current solution by taking advantage of design flexibility and advanced power management technology provided by the ARM MPCore technology. Restricted and mobile power budgets keep running. With scalable maximum performance, the processor can surpass the performance of today's similar high-performance embedded devices and enable a stable software investment based on broadening the market.
In addition to single-core and multi-core soft macros, the commonly used dual-core configuration can also be used as a hard macro implementation of the TSMC 40G/GL process, thereby minimizing the time to market for high-performance Cortex-A9 processors and reducing the risks associated with their listing. cost. Utilizing optimized ARM physical IP and advanced implementation technologies, this hard macro can be used as a power optimization implementation or performance optimization implementation
Speed ​​optimization
Speed-optimized hard macro implementation provides system designers with integrated low-power technology for the industry-standard ARM processor, extending ARM's performance leadership to the power envelope required in a compact, high-density, thermally-constrained environment. High-margin consumer equipment and corporate equipment. After selecting this hard macro implementation from standard silicon, its operating frequency exceeds 2 GHz, representing an ideal solution for performance-oriented, high-margin applications.
Power optimization
In many thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer applications and high-density enterprise applications, energy efficiency is paramount. After the Cortex-A9 power-optimized hard macro implementation was selected from standard silicon, it offered a maximum performance of 4000 DMIPS, while each CPU consumed less than 250 mW.
This hard macro implementation includes high-performance system components that are compliant with the ARM AMBA standard to maximize data communications speed while minimizing power consumption and silicon area. Each Cortex-A9 hard macro implementation also includes the CoreSightTM Program Trace Macrocell (PTM), which makes the processor's instruction stream completely visible, enabling members of the software community to develop code that optimizes performance. In addition, this macro also includes the ARM high performance L2 cache controller, which supports configuration with L2 cache memory between 128K and 8M.
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