1 Introduction
At present, there is a large demand for near-infrared detection and imaging in industrial, medical, astronomical and military. This paper introduces a new high-gain GaAs/InGaAs quantum photodetector that responds to near-infrared. Firstly, the IV characteristics of the detector were tested and discussed. When the detector bias voltage was -1.5V, the response rate was greater than 10A/W, and the response rate decreased with the increase of illumination power. The 2&TImes; 8-element readout circuit is designed for detector characteristics and detector array size. The sample after docking of the detector and readout circuit operates at 77K. The detector bias voltage is -1.5V, and the detector rate reaches 1.38 & TImes; 1010cmHz 1/2/W when the integration time is 200μs, which meets the requirements of practical applications. In order to verify the practicability of the detector and readout circuit and the docking sample, the data acquisition card and imaging system were designed and the test results were given.
2. Detector and readout circuit
2.1 detector
The IV characteristics of the detector can provide an important basis for the design of the readout circuit. For this purpose, the detector characteristics are tested on the optoelectronic test platform using the keithley 4200-SCS semiconductor characteristic tester. The detector array is 2 & TImes; 8 yuan, the unit detector area is 80 & TImes; 80 μm. The substrate potential as a common electrode is fixed during the test, and the voltage at one end of the detector unit is scanned.
Figure 1 shows the I-V characteristics of the device. Unlike the QWIP device, the characteristic curve is clearly asymmetrical. The detector has a threshold voltage of -0.8V. The response current increases rapidly after the detector bias voltage is greater than -0.8V. The corresponding current changes slowly with the bias voltage in the range of -0.8V~-3V. The detector response current is relatively small when forward biased. When the test is 77K, the dark current of the detector is less than 10-13A at -1.5V, and the dark current is small, which is beneficial to reduce noise and improve detection rate and signal-to-noise ratio. The CV characteristic measured the capacitance of the detector to be about 7.5pF.
Figure 2 shows the response rate of the detector at different illumination powers. The results show that the response rate of the detector is much larger than 1A/W, and the response rate is greater than 10A/W when the bias voltage is -1V, indicating that the quantum efficiency and photoelectric gain of the detector are large. The test results also show that the detector's response rate decreases with increasing illumination power. This feature helps to improve the dynamic range of the imaging system.
The working bias of the detector has a significant impact on the focus plane operation and requires careful selection and strict control.
Figure 3 shows that the dynamic impedance is large when the detector bias voltage is -1V, and the large dynamic impedance indicates that the detector response current changes little with the operating bias voltage, which reduces the stability requirement of the detector operating bias and improves the detector array response. Consistency. Therefore, the detector array is connected to the readout circuit and then -1V is selected as the operating voltage.
2.2 readout circuit
The readout circuit is designed according to the characteristics of the detector. The structure is shown in Figure 4. It includes a row select switch, a capacitive transimpedance amplifier (CTIA), a correlated double sampling circuit (CDS), a column select switch, and an output buffer. Using the CTIA structure as a column amplifier can stabilize the detector operating bias, improve injection efficiency and linearity, and the CDS circuit can suppress fixed pattern noise.
The readout circuit works as follows: First, a row of detectors is connected to the CTIA column amplifier, and then the column amplifier is reset to discharge the integrated capacitor, and the potential of the upper electrode of the detector is reset to the reset potential. After reset, the column amplifier begins to integrate, and the CDS circuit samples and holds the reset signal and the integrated signal of the column amplifier. Finally, the sample-and-hold circuit is sequentially strobed under the control of the column selection switch, and eight detector integration signals are sequentially output through the output buffer.
The above readout process is then repeated to begin the reading of another row of detectors.
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