How are DDR line width and impedance determined during PCB design?
Let's learn through a specific project.
PCB design requirements given by the original manufacturer of one of the above development boards. The PCB adopts a 6-layer laminate design with a thickness of 1.6mm. The inner layer is formed by pressing two 4MIL copper-containing core plates, and a copper-free core plate and two prepregs 2116 are filled between the core plates, mainly to adjust the thickness of 1.6MM. Layers 1 to 2 and layers 6 to 5 are filled with prepreg 1080, and the thickness after pressing is 2.7MIL.
I found the information of the core board and prepreg on the Internet, and the parameters are basically consistent with the parameters given by the original manufacturer.
After confirming the information provided by the original manufacturer, let's use the software to calculate whether the line width and impedance can be matched.
The DDR3 signal transmission line running on the outer layer has a line width of 3.5Mil, a height of 2.7Mil to the reference plane, and an impedance of 55Ohm. The software verification is as follows:
The calculated value from the software is 49.27 Ohm, which is somewhat different from the 55 Ohm given by the original manufacturer.
The DDR3 differential signal transmission line running on the outer layer has a line width of 4Mil, a height of 2.7Mil to the reference plane, and an impedance of 100Ohm. The software verification is as follows:
The calculated value of the software is 89.9 Ohm, which is somewhat different from the 100 Ohm given by the original manufacturer.
Through the above method, we probably know how the DDR line width and impedance are determined. When we design DDR ourselves in the future, we can use this method to determine the line width of the DDR and the stacking situation of the PCB board, so that the performance of the board we design is better and more stable.
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