To use low-cost 32-bit microcontrollers, developers face two choices, based on the Cortex-M3 core or the ARM7TDMI core. How to make a choice? What is the selection criteria? This article mainly introduces some features of the ARM Cortex-M3 core microcontroller different from ARM7, to help you quickly choose.
1. ARM implementation
The ARM Cortex-M3 is a new ARM embedded core based on the ARM V7 architecture. It uses a Harvard architecture and uses separate instruction and data buses (with a bus under the von Neumann architecture, data and instructions). In essence, the Harvard structure is physically more complex, but the processing speed is significantly faster. According to Moore's theorem, complexity is not a very important thing, and the increase in throughput is extremely valuable.
ARM's positioning of the Cortex-M3 is to provide low-cost, low-power chips to the professional embedded market. In terms of cost and power consumption, the Cortex-M3 has quite good performance, and ARM believes it is particularly suitable for automotive and wireless communications. Like all ARM cores, ARM licenses the design to individual manufacturers to develop specific chips. To date, several chip manufacturers have begun to produce microcontrollers based on the Cortex-M3 core.
The ARM core of the ARM7TDMI (including the ARM7TDMIS) series is also oriented to the same market. This type of kernel has been around for more than a decade and has driven ARM to become a leader in processor cores. Numerous manufacturers (as claimed by ARM, up to 16) sell ARM7-based processors and other supporting system software, development and debugging tools. In many ways, the ARM7TDMI can be called a do-it-yourself in the embedded world.
2. Difference between the two
In addition to using the Harvard architecture, the Cortex-M3 has other significant advantages: it has a smaller base kernel, lower price, and faster speed. Integrated with the core are system peripherals such as interrupt controllers, bus matrices, and debug function blocks, which are typically added by chip manufacturers. The Cortex-M3 also integrates a sleep mode and an optional full eight-zone memory protection unit. It uses the THUMB-2 instruction set to minimize assembler usage.
3. Instruction Set
ARM7 can use both ARM and Thumb instruction sets, while Cortex-M3 only supports the latest Thumb-2 instruction set. The advantages of this design are:
Eliminating the need to switch between Thumb and ARM code, this state switch can degrade performance for earlier processors.
The Thumb-2 instruction set is designed for the C language and includes the If/Then structure (predicting conditional execution of the next four statements), hardware partitioning, and local status operations.
The Thumb-2 instruction set allows users to maintain and modify applications at the C code level, and the C code portion is very easy to reuse.
The Thumb-2 instruction set also includes the ability to call assembly code: Luminary believes that it is not necessary to use any assembly language.
By combining these advantages, the development of new products will be easier to implement and the time to market will be greatly shortened.
4. Interrupt
Another innovation of the Cortex-M3 is the Nested Vector Interrupt Controller (NVIC). Compared to the external interrupt controller used by ARM7, the Cortex-M3 core integrates an interrupt controller that can be configured by the chip manufacturer to provide basic 32 physical interrupts with 8 levels of priority and up to 240 physics. Interrupt and 256 interrupt priority levels. This type of design is deterministic and has low latency, making it ideal for automotive applications.
NVIC uses a stack-based exception model. When the interrupt is processed, the program counter, program status register, link register, and general-purpose register are pushed onto the stack, and after the interrupt processing is completed, these registers are restored. Stack processing is done in hardware, eliminating the need to create an interrupt service stack operation in assembly language.
Interrupt nesting can be implemented. Interrupts can be changed to a higher priority than the previous service program, and the priority status can be changed at runtime. The use of tail-chaining continuous interrupt technology consumes only three clock cycles, which reduces latency and improves performance compared to continuous voltage and stacking of 32 clock cycles.
If the NVIC has already pushed the stack before the higher priority interrupt arrives, then only a new vector address is needed to service the higher priority interrupt. Similarly, NVIC does not use stack operations to service new interrupts. This approach is completely deterministic and has low latency.
5. Sleep
The Cortex-M3's power management solution supports three sleep modes: Sleep Now, Sleep on Exit (Stop Minimum Priority ISR) and SLEEPDEEP modes via NVIC. In order to generate periodic interrupt intervals, the NVIC also integrates a system tick timer, which can also be used as a heartbeat for RTOS and scheduled tasks. The difference between this approach and the previous ARM architecture is that no external clock is required.
6. Memory protection unit
The memory protection unit is an optional component. With this option selected, the memory area can be tied to the application-specific process according to the rules defined by other processes. For example, some memory can be completely blocked by other processes, while another part of the memory can be read-only for some processes. It is also possible to prohibit processes from entering the memory area. Reliability, especially real-time, has therefore been significantly improved.
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