With the rapid development of electronic technology and the wide application of wireless communication technology in various fields, high frequency, high speed and high density have gradually become one of the significant development trends of modern electronic products. High-frequency signal transmission and high-speed digitization force the PCB to move toward micro-holes and buried/blind holes, fine wires, and uniform thinning of dielectric layers. High-frequency high-speed and high-density multilayer PCB design technology has become an important research field. Based on years of experience in hardware design work, the author summarizes the design techniques and precautions of some high-frequency circuits for your reference.
High-frequency high-speed high-density multilayer PCB design technology
1. How to choose PCB board?
Choosing PCB boards must strike a balance between meeting design requirements and mass production and cost. Design requirements include both electrical and institutional components. This material problem is usually more important when designing very high speed PCB boards (greater than GHz). For example, the commonly used FR-4 material, dielectric loss at several GHz frequencies can have a large impact on signal attenuation and may not be useful. As far as electrical is concerned, it is important to note whether the dielectric constant and the dielectric loss are combined at the designed frequency.
2. How to avoid high frequency interference?
The basic idea of ​​avoiding high-frequency interference is to minimize the interference of high-frequency signal electromagnetic fields, which is called crosstalk. You can use the distance between the high-speed signal and the analog signal, or add ground guard/shunt traces next to the analog signal. Also pay attention to the digital ground noise interference to the analog ground.
3. How to solve signal integrity problems in high-speed design?
Signal integrity is basically a matter of impedance matching. The factors affecting the impedance matching are the architecture of the signal source and the output impedance, the characteristic impedance of the trace, the characteristics of the load end, and the topology of the trace. The solution is to terminate and adjust the topology of the trace.
4. How is the differential wiring method implemented?
There are two points to note for the wiring of the differential pair. One is that the length of the two lines should be as long as possible, and the other is that the spacing between the two lines (which is determined by the differential impedance) should remain the same, that is, to be parallel. There are two ways of paralleling. One is that the two lines are on the same side-by-side, and the other is two lines that are on the top-by-side. In general, the side-by-side (side-by-side, side-by-side) implementation is more common.
5. How to implement differential wiring for a clock signal line with only one output?
To use differential routing, it must be meaningful that both the source and the receiver are differential signals. Therefore, differential wiring cannot be used for a clock signal with only one output.
6. Can I add a matching resistor between the differential pairs at the receiving end?
The matching resistance between the differential pair of the receiving end is usually added, and its value should be equal to the value of the differential impedance. This signal quality will be better.
7. Why is the wiring of the differential pair close and parallel?
The wiring of the differential pairs should be properly close and parallel. The proper proximity is because this spacing affects the value of the differential impedance, which is an important parameter for designing differential pairs. Parallelism is also required because the consistency of the differential impedance is maintained. If the two lines are too close, the differential impedance will be inconsistent, which will affect signal integrity and timing delay.
8. How to deal with some theoretical conflicts in actual wiring?
Basically, it is right to isolate the analog/digital partitions. It should be noted that the signal trace should not cross the moat as much as possible, and do not let the return current path of the power supply and signal become too large.
The crystal oscillator is an analog positive feedback oscillator circuit. To have a stable oscillation signal, the loop gain and phase specifications must be met. The oscillation specifications of the analog signal are easily disturbed, and even ground guard traces may not completely isolate the interference. And too far away, the noise on the ground plane will also affect the positive feedback oscillator circuit. Therefore, be sure to bring the distance between the crystal and the chip closer.
There are many conflicts between high-speed wiring and EMI requirements. However, the basic principle is that the electrical resistance of the EMI or the ferrite bead cannot cause some electrical characteristics of the signal to fail to meet the specifications. Therefore, it is best to use the techniques of routing and PCB stacking to solve or reduce EMI problems, such as high-speed signals going inside. Finally, use resistors or ferrite bead to reduce the damage to the signal.
9. How to solve the contradiction between manual wiring and automatic wiring of high-speed signals?
Most of the autorouters of the current wiring software have set constraints to control the winding method and the number of vias. The EDA company's winding engine capabilities and constraints are sometimes far from being set. For example, is there a sufficient constraint to control the serpentine 蜿蜒, whether it can control the spacing of the differential pairs, and so on. This will affect whether the routing method that is automatically routed can meet the designer's ideas. In addition, the difficulty of manually adjusting the wiring is also absolutely related to the ability of the winding engine. For example, the ability to push the line, the ability to push through the hole, and even the ability of the wire to push the copper. Therefore, choosing a router with a strong winding engine is the solution.
10. About the test coupon.
The test coupon is used to measure the characteristic impedance of the PCB produced by TDR (Time Domain Reflectometer) to meet the design requirements. Generally, the impedance to be controlled has a single line and a differential pair. Therefore, the trace line width and line spacing (with differential pairs) on the test coupon should be the same as the line to be controlled. The most important thing is the position of the grounding point when measuring. In order to reduce the inductance of the ground lead, the TDR probe is usually grounded very close to the probe tip, so the distance and way of measuring the signal's point to the ground point on the test coupon To match the probe used.
11. In high-speed PCB design, the blank area of ​​the signal layer can be coated with copper, and how should the copper of multiple signal layers be distributed on the ground and the power supply?
Generally, most of the copper in the blank area is grounded. Just pay attention to the distance between the copper and the signal line when applying copper next to the high-speed signal line, because the copper applied will reduce the characteristic impedance of the trace. Also be careful not to affect the characteristic impedance of its layer, such as in the structure of a dual strip line.
12. Is it possible to calculate the characteristic impedance using the microstrip line model on the signal line above the power plane? Can the signal between the power supply and the ground plane be calculated using the stripline model?
Yes, both the power plane and the ground plane must be considered as reference planes when calculating the characteristic impedance. For example, a four-layer board: top layer - power layer - ground layer - bottom layer, then the model of the top trace characteristic impedance is a microstrip line model with the power plane as a reference plane.
13. Automatically generate test points through high-density printed boards through software. Under normal circumstances, can it meet the test requirements for mass production?
Whether the general software automatically generates test points to meet the test requirements must see whether the specifications of the test points meet the requirements of the test equipment. In addition, if the wiring is too dense and the specification of the test points is strict, there may be no way to automatically add test points to each line. Of course, it is necessary to manually fill in the places to be tested.
14. Does adding test points affect the quality of high-speed signals?
As for whether it will affect the signal quality, it depends on how the test points are added and how fast the signal is. Basically added test points (without vias or DIP pins as test points) may be added online or pulled a short line from the line. The former is equivalent to adding a small capacitor on the line, while the latter is a branch. Both of these conditions will affect the high-speed signal more or less, and the degree of influence is related to the frequency speed of the signal and the edge rate of the signal. The size of the impact can be seen through simulation. In principle, the smaller the test point, the better (and of course the requirements of the test tool). The shorter the branch, the better.
15. How many PCBs form the system, and how should the ground wires between the boards be connected?
When the signal or power supply between the PCB boards is connected, for example, the A board has power or signal sent to the B board, there must be an equal amount of current flowing from the ground to the A board (this is the Kirchoff current law). The current on this formation will flow back where the impedance is the least. Therefore, at each interface where the power source or signal is connected to each other, the number of pins allocated to the ground layer should not be too small to reduce the impedance, which can reduce the noise on the ground layer. In addition, you can also analyze the entire current loop, especially the larger current, adjust the ground or ground connection to control the current travel (for example, make a low impedance somewhere, let most of the current from this Place to reduce the impact on other sensitive signals.
16. Can you introduce some foreign technical books and data on high-speed PCB design?
Applications for high-speed digital circuits today include communications networks and calculators. In terms of communication networks, the working frequency of the PCB has reached GHz, and the number of stacks is as much as 40 layers. Calculator-related applications are also due to advances in chips. Whether it is a general PC or a server, the maximum operating frequency on the board has reached 400MHz (such as Rambus). In response to this high-speed, high-density wiring requirement, the demand for blind/buried vias, mircrovias, and build-up process processes is also increasing. These design requirements are available to manufacturers in large quantities.
17. Two characteristic impedance equations that are often referred to:
Microstrip Z={87/[sqrt(Er+1.41)]}ln[5.98H/(0.8W+T)] where W is the line width, T is the copper thickness of the trace, and H is The distance from the trace to the reference plane, Er is the dielectric constant of the PCB material. This formula must be applied in the case of 0.1<(W/H)<2.0 and 1<(Er)<15.
Stripline Z=[60/sqrt(Er)]ln{4H/[0.67Ï€(T+0.8W)]} where H is the distance between the two reference planes and the trace is in the middle of the two reference planes . This formula must be applied with W/H<0.35 and T/H<0.25.
18. Can the ground wire be added in the middle of the differential signal line?
In the middle of the differential signal, the ground line cannot be added. Because the most important point of application of differential signals is the benefits of mutual coupling between differential signals, such as flux cancellation, noise immunity, and the like. If the ground wire is added in the middle, the coupling effect will be destroyed.
19. Does the rigid flexible board design require special design software and specifications? Where can I undertake this type of circuit board processing in China?
A flexible printed circuit can be designed using software that generally designs PCBs. The same is done in the Gerber format for FPC manufacturers. Because the manufacturing process is different from the general PCB, each manufacturer will have restrictions on the minimum line width, minimum line spacing, and minimum aperture depending on their manufacturing capabilities. In addition, some copper can be reinforced at the turning point of the flexible circuit board. As for the manufacturer of the product, the online "FPC" can be found as a keyword query.
20. What are the principles for properly selecting the point at which the PCB and the case are grounded?
The principle of selecting the PCB and case ground point selection is to use chassis ground to provide a low impedance path to the return current and the path to control this return current. For example, the ground plane of the PCB can be connected to the chassis ground by a fixed screw near the high-frequency device or the clock generator to minimize the entire current loop area and reduce electromagnetic radiation.
21, the circuit board DEBUG should start from those aspects?
In the case of digital circuits, first determine three things in order: 1. Verify that all power supply values ​​are within the design requirements. Some systems with multiple power supplies may require some specification of the order and speed of some power supplies. 2. Verify that all clock signal frequencies are working properly and that there are no non-monotonic problems on the edges of the signal. 3. Verify that the reset signal meets the specifications. If these are normal, the chip should signal the first cycle. Next, follow the system operation principle and the bus protocol to debug.
22, in the case of fixed circuit board size, if the design needs to accommodate more functions, it is often necessary to increase the PCB trace density, but this may lead to increased mutual interference of the traces, while the traces are too thin and the impedance Can't be reduced, ask experts to introduce techniques in high-speed (>100MHz) high-density PCB design?
Crosstalk interference is of particular concern when designing high-speed, high-density PCBs because it has a large impact on timing and signal integrity. Here are a few caveats:
Controls the continuity and matching of the trace characteristic impedance.
The size of the trace spacing. The spacing commonly seen is twice the line width. The simulation can be used to know the influence of the trace spacing on timing and signal integrity, and to find the minimum tolerance that can be tolerated. The results of different chip signals may vary.
Choose the appropriate termination method.
Avoid the same direction of the upper and lower adjacent layers, even if the traces overlap exactly above and below, because this crosstalk is larger than the situation of adjacent lines in the same layer.
Blind/buried vias are used to increase the trace area. However, the manufacturing cost of the PCB will increase. It is really difficult to achieve full parallelism and equal length in actual implementation, but still try to do it.
In addition, differential termination and common-mode termination can be reserved to mitigate the effects on timing and signal integrity.
23. The filtering at the analog power supply is often done with an LC circuit. But why is LC sometimes worse than RC filtering?
The comparison of LC and RC filtering effects must consider whether the selection of the frequency band and inductance value to be filtered is appropriate. Because the inductance of the inductor is related to the inductance value and frequency. If the noise frequency of the power supply is low and the inductance value is not large enough, the filtering effect may not be as good as RC. However, the cost of using RC filtering is that the resistor itself consumes energy, is inefficient, and pays attention to the power that the selected resistor can withstand.
24, the choice of inductors when filtering, what is the method of capacitance value?
In addition to considering the noise frequency that you want to filter out, you should consider the response capability of the instantaneous current. If the output of the LC has a chance to output a large current instantaneously, the large value of the inductor will hinder the speed at which this large current flows through the inductor and increase the ripple noise. The value of the capacitor is related to the magnitude of the ripple noise specification that can be tolerated. The smaller the ripple noise value is, the larger the capacitance value will be. The ESR/ESL of the capacitor also has an effect. In addition, if the LC is placed at the output of the switching regulation power, note the effect of the pole/zero generated by the LC on the loop stability of the negative feedback control. .
25. How to achieve EMC requirements as much as possible without causing too much cost pressure?
The increased cost of EMC due to EMC on the PCB is usually due to the increased number of formations to enhance the shielding effect and increase the suppression of high frequency harmonics such as ferrite bead and choke. In addition, it is usually necessary to match the shielding structure of other mechanisms to make the whole system pass the EMC requirements. The following is only a few of the PCB design techniques to provide electromagnetic radiation effects that reduce the circuit.
Whenever possible, use a device with a slower slew rate to reduce the high frequency components produced by the signal.
Pay attention to the location of the high frequency device, not too close to the external connector.
Pay attention to the impedance matching of high-speed signals, the trace layer and its return current path to reduce high-frequency reflections and radiation.
Place enough decoupling capacitors on the power pins of each device to mitigate noise on the power plane and ground plane. Pay particular attention to whether the frequency response and temperature characteristics of the capacitor meet the design requirements.
The ground near the external connector can be properly segmented with the ground plane and the ground of the connector can be connected to the chassis ground.
Ground guard/shunt traces can be used as appropriate for some very high speed signals. But pay attention to the effect of guard/shunt traces on the trace characteristic impedance.
The power plane is 20H less than the ground, and H is the distance between the power plane and the ground.
26. When there are multiple digital/analog function blocks in a PCB board, the conventional practice is to separate the digital/analog grounds. What are the reasons?
The reason for separating the digital/analog ground is because the digital circuit generates noise at the power supply and ground when switching between high and low potentials, and the magnitude of the noise is related to the speed and current of the signal. If the ground plane is not divided and the noise generated by the digital area circuit is large and the circuits of the analog area are very close, the analog signal will still be disturbed by the ground noise even if the digital-to-analog signals do not cross. That is to say, the method of digitally undivided can only be used when the analog circuit area is far away from the digital circuit area where large noise is generated.
27. Another method is to ensure that the digital/analog separate layout, and the digital/analog signal traces do not cross each other, the entire PCB board is not divided, and the digital/analog ground is connected to the ground plane. What is the truth?
The requirement that the digital-to-analog signal traces cannot be crossed is because the digital signal whose speed is slightly faster will return to the source of the digital signal along the ground near the lower side of the trace as much as possible. When crossed, the noise generated by the return current will appear in the analog circuit area.
28. How to consider impedance matching when designing high-speed PCB design schematics?
Impedance matching is one of the design elements when designing high speed PCB circuits. The impedance value has an absolute relationship with the routing method, such as walking on the surface layer (microstrip) or inner layer (stripline/double stripline), distance from the reference layer (power layer or ground layer), trace width, PCB material, etc. Both will affect the characteristic impedance value of the trace. That is to say, the impedance value can be determined after wiring. General simulation software can not consider some non-continuous wiring conditions due to the limitation of the line model or the mathematical algorithm used. At this time, only some terminators, such as series resistors, can be reserved on the schematic. Moderate the effect of discontinuity in the trace impedance. The only way to solve the problem is to pay attention to avoiding impedance discontinuities.
29. Where can I provide a more accurate IBIS model library?
The accuracy of the IBIS model directly affects the results of the simulation. Basically, IBIS can be regarded as the electrical characteristic data of the actual chip I/O buffer equivalent circuit. It can be converted from SPICE model (can also use measurement, but more restrictions), while SPICE data and chip manufacturing have absolute Relationship, so the same device is provided by different chip manufacturers, the SPICE data is different, and the data in the converted IBIS model will also be different. That is to say, if the A manufacturer's devices are used, only they have the ability to provide accurate model data for their devices, because no one else knows better than them what process their devices are made of. If the IBIS provided by the manufacturer is inaccurate, it is the fundamental solution to continuously ask the manufacturer to improve.
30. In high-speed PCB design, should designers consider the rules of EMC and EMI from those aspects?
In general EMI/EMC design, both radiated and conducted aspects need to be considered. The former belongs to the higher frequency part (>30MHz) and the latter is the lower frequency part (<30MHz). So you can't just pay attention to the high frequency and ignore the low frequency part. A good EMI/EMC design must be based on the location of the device, the layout of the PCB stack, the important way to move the device, the choice of the device, etc., if these are not better arranged beforehand, afterwards It will take half the effort and increase the cost. For example, the position of the clock generator should not be close to the external connector. The high-speed signal should go as far as possible to the inner layer and pay attention to the characteristic impedance matching and the continuity of the reference layer to reduce the reflection. The slope of the signal pushed by the device (slew rate As small as possible to reduce high frequency components, choose decoupling/bypass capacitors to pay attention to whether the frequency response meets the requirements to reduce power layer noise. In addition, pay attention to the return path of the high-frequency signal current so that the loop area is as small as possible (that is, the loop impedance is as small as possible) to reduce the radiation. It is also possible to divide the formation to control the range of high frequency noise. Finally, properly select the chassis ground of the PCB and the enclosure.
31, how to choose EDA tools?
In the current pcb design software, thermal analysis is not a strong point, so it is not recommended. Other functions 1.3.4 can choose PADS or Cadence performance price ratio is good. Beginners of PLD design can use the integrated environment provided by PLD chip manufacturers, and can use single point tools when designing more than one million gates.
32. Please recommend an EDA software suitable for high speed signal processing and transmission.
With conventional circuit design, INNOVEDA's PADS is very good, and there are simulation software that works together, and this type of design often occupies 70% of applications. In high-speed circuit design, analog and digital hybrid circuits, Cadence's solution should be a relatively good performance software. Of course, Mentor's performance is still very good, especially its design process management should be the best. (Da Tang Telecom Technology Expert Wang Sheng)
33. What is the meaning of the various layers of the PCB?
Topoverlay - the name of the top device, also known as top silkscreen or top component legend, such as R1 C5,
IC10.bottomoverlay--common multi-layer--If you design a 4-layer board, you place a free pad or via, define it as multilay, then its pad will automatically appear on 4 layers, if you only define it Top layer, then its pad will only appear on the top layer.
34, 2G above high-frequency PCB design, routing, typesetting, what should be paid attention to?
High-frequency PCBs above 2G are RF circuit designs and are not covered by high-speed digital circuit design. The layout and routing of the RF circuit should be considered together with the schematic, as the layout will cause a distribution effect. Moreover, the RF circuit design of some passive components is realized by parameterized definition, special shape copper foil, so EDA tools are required to provide parametric devices and to edit special shape copper foil. Mentor's boardstation has dedicated RF design modules to meet these requirements. Moreover, general RF design requires specialized RF circuit analysis tools. The industry's best known is agilent's eesoft, which has a good interface with Mentor's tools.
35, 2G or higher high-frequency PCB design, what rules should be followed in the design of microstrip?
RF microstrip line design requires 3D field analysis tools to extract transmission line parameters. All rules should be specified in this field extraction tool.
36. For a full digital signal PCB, there is an 80MHz clock source on the board. In addition to the use of wire mesh (grounding), what circuit should be used to protect it in order to ensure sufficient driving capability?
To ensure that the drive capability of the clock should not be achieved through protection, a clock driver chip is generally used. The general concern about clock drive capability is due to multiple clock loads. Using a clock driver chip, a clock signal is turned into several, using a point-to-point connection. Select the driver chip, in addition to ensuring a basic match with the load, the signal edge meets the requirements (generally the clock is along the valid signal). When calculating the system timing, it is necessary to count the clock delay in the driver chip.
37. If a separate clock signal board is used, what kind of interface is generally used to ensure that the transmission of the clock signal is less affected?
The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board increases the signal routing length. Moreover, the grounding power supply of the board is also a problem. For long distance transmission, a differential signal is recommended. The LVDS signal can meet the drive capability requirements, but your clock is not too fast and not necessary.
38, 27M, SDRAM clock line (80M-90M), the second and third harmonics of these clock lines are just in the VHF band, and the interference is very high after the high frequency input from the receiving end. In addition to shortening the line length, what better way?
If the third harmonic is large, the second harmonic is small, probably because the signal duty cycle is 50%, because in this case, the signal has no even harmonics. At this time, you need to modify the signal duty cycle. In addition, for a clock signal that is unidirectional, source-side series matching is generally used. This suppresses secondary reflections but does not affect the clock edge rate. The source matching value can be obtained by the formula below.
39. What is the topology of the trace?
Topology, some is also called routing order, the routing order for networks with multi-port connections.
40. How to adjust the topology of the trace to improve signal integrity?
This kind of network signal direction is more complicated, because the unidirectional, bidirectional signal, different level signal, the topology effect is different, it is difficult to say which topology is beneficial to the signal quality. Moreover, when doing pre-simulation, what kind of topology is used is very demanding for engineers, and it is required to understand the circuit principle, signal type, and even wiring difficulty.
41, how to reduce the EMI problem by arranging the laminate?
First of all, EMI should be considered from the system, and the PCB alone cannot solve the problem. For EMI, I think it is mainly to provide the shortest return path of the signal, reduce the coupling area, and suppress differential mode interference. In addition, the ground layer is tightly coupled to the power layer, which is more suitable than the power layer to suppress common mode interference.
42. Why do you want to lay copper?
There are several reasons for copper plating. 1, EMC. For a large area of ​​ground or power copper, it will play a shielding role, and some special, such as PGND to protect. 1, PCB process requirements. Generally, in order to ensure the plating effect, or the laminate is not deformed, copper is laid for the PCB layer with less wiring. 3, signal integrity requirements, give a high-frequency digital signal a complete return path, and reduce the wiring of the DC network. Of course, there are heat dissipation, special device installation requires copper plating and so on.
43. In a system, including dsp and pld, what problems should I pay attention to when wiring?
Look at the ratio of your signal rate to the length of the wiring. If the signal is comparable to the time delay of the transmission line and the time of the signal change, consider the signal integrity problem. In addition, for multiple DSPs, clocks, data signal traces will also affect signal quality and timing, and need attention.
44. In addition to protel tool wiring, are there other good tools?
As for the tools, in addition to PROTEL, there are many wiring tools, such as MENTOR's WG2000, EN2000 series and powerpcb, Cadence's allegro, zuken's cadstar, cr5000, etc., each with its own strengths.
45. What is the “signal return path�
Signal return path, that is, return current. When a high-speed digital signal is transmitted, the signal flows from the driver along the PCB transmission line to the load, and then the load returns to the driver through the shortest path along the ground or power source. This return signal on the ground or power supply is called the signal return path. Dr. Johson explained in his book that high-frequency signal transmission is actually the process of charging the dielectric capacitor between the transmission line and the DC layer. SI analyzes the electromagnetic properties of this paddock and the coupling between them.
46, how to perform SI analysis on the connector?
In the IBIS 3.2 specification, there is a description of the connector model. The EBD model is generally used. If it is a special board, such as a backplane, a SPICE model is required. Multi-board simulation software (HYPERLYNX or IS_multiboard) can also be used. When building a multi-board system, the distribution parameters of the input connectors are generally obtained from the connector manual. Of course, this method will not be accurate enough, but as long as it is within an acceptable range.
47. What are the methods of termination?
Terminal, also known as matching. The active end matching and the terminal matching are generally classified according to the matching position. The source-side matching is generally a series matching of resistors. The terminal matching is generally parallel matching. There are many ways, such as resistance pull-up, resistor pull-down, Dyvenan matching, AC matching, and Schottky diode matching.
48. What is the factor of termination (matching)?
The matching mode is generally determined by the BUFFER characteristics, the topology, the type of the level, and the decision mode. The duty cycle of the signal and the power consumption of the system are also considered.
49. What are the rules for using termination (matching)?
The most critical aspect of digital circuits is the timing problem. The purpose of the matching is to improve the signal quality and obtain a determinable signal at the decision time. For the level effective signal, the signal quality is stable under the premise of ensuring the establishment and holding time; for the delay effective signal, the signal change delay speed meets the requirements under the premise of ensuring the signal delay monotonicity. Some information about matching is available in the Mentor ICX product textbook. In addition, "High Speed ​​Digital design a hand book of blackmagic" has a chapter dedicated to the terminal, from the electromagnetic wave principle to describe the role of matching on signal integrity, for reference.
50. Can I simulate the logic function of the device using the IBIS model of the device? If not, how do you perform board level and system level simulation of the circuit?
The IBIS model is a behavioral model and cannot be used for functional simulation. Functional simulation requires a SPICE model or other structural level model.
51. In the system where digital and analog coexist, there are 2 kinds of processing methods, one is to separate the digital ground and the analog ground. For example, in the ground layer, the digital ground is an independent piece, and the analog ground is independent. The single point is copper or FB magnetic. The beads are connected, and the power supply is not separated; the other is that the analog power supply and the digital power supply are connected separately by FB, and the ground is uniformly. May I ask Mr. Li, are the two methods the same effect?
It should be said that it is the same in principle. Because the power supply and ground are equivalent to high frequency signals.
The purpose of distinguishing the analog and digital parts is to prevent interference, mainly the interference of digital circuits to analog circuits. However, the segmentation may cause the signal return path to be incomplete, affecting the signal quality of the digital signal and affecting the system EMC quality. Therefore, no matter which plane is divided, it depends on whether the signal return path is increased and how much the recirculation signal interferes with the normal working signal. There are also some hybrid designs, regardless of the power supply and ground. In the layout, the layout is separated according to the digital part and the analog part to avoid cross-region signals.
52. Safety issues: What is the specific meaning of FCC and EMC?
FCC: federal communication commission EMC: electro megnetic compatibility Electromagnetic compatibility FCC is a standards organization and EMC is a standard. Standards are issued with corresponding reasons, standards and test methods.
53. What is differential wiring?
Differential signals, some of which are also called differential signals, use two identical signals with opposite polarities to transmit one channel of data, relying on the difference between the two signal levels. In order to ensure that the two signals are completely consistent, parallelism should be maintained during wiring, and the line width and line spacing remain unchanged.
54. What are the PCB simulation software?
There are many types of simulations, and high-speed digital circuit signal integrity analysis and simulation (SI) commonly used software are icx, signalvision, hyperlynx, XTK, speectraquest and so on. Some also use Hspice.
55. How does the PCB simulation software perform LAYOUT simulation?
In high-speed digital circuits, in order to improve signal quality and reduce wiring difficulty, a multi-layer board is generally used to allocate a dedicated power layer and a ground layer.
56. How to deal with the layout and wiring to ensure the stability of signals above 50M?
The key to high-speed digital signal routing is to reduce the impact of the transmission line on signal quality. Therefore, the high-speed signal layout above 100M requires the signal trace to be as short as possible. In digital circuits, high-speed signals are defined by the signal rise time. Moreover, different types of signals (such as TTL, GTL, LVTTL), the method of ensuring signal quality is different.
57. The RF part of the outdoor unit, the IF part, and even the low-frequency circuit part that monitors the outdoor unit are often deployed on the same PCB. What are the requirements on the material of such a PCB? How to prevent interference between RF, IF and even low frequency circuits?
Hybrid circuit design is a big problem. It's hard to have a perfect solution.
Generally, the RF circuit is laid out as a separate single board in the system, and even a special shielding cavity is provided. Moreover, the RF circuit is generally single-sided or double-sided, and the circuit is relatively simple, all of which are designed to reduce the influence on the distribution parameters of the RF circuit and improve the consistency of the RF system. Compared with the general FR4 material, the RF circuit board tends to be a substrate with a high Q value. The dielectric constant of this material is relatively small, the transmission line distribution capacitance is small, the impedance is high, and the signal transmission delay is small. In the hybrid circuit design, although the RF and digital circuits are on the same PCB, they are generally divided into a RF circuit area and a digital circuit area, and are respectively arranged and routed. Shielded between grounded vias and shielded boxes.
58. For the RF part, the IF part and the low frequency circuit part are deployed on the same PCB. What solution does the mentor have?
Mentor's board-level system design software includes a dedicated RF design module in addition to basic circuit design features. In the RF schematic design module, a parametric device model is provided, and a bidirectional interface with an RF circuit analysis simulation tool such as EESOFT is provided; in the RF LAYOUT module, a pattern editing function dedicated to the layout of the RF circuit is provided, and The bidirectional interface of the RF circuit analysis and simulation tool such as EESOFT can reverse the schematic and PCB for the analysis and simulation results. At the same time, with the design management function of Mentor software, design reuse, design derivation, and collaborative design can be easily realized. Greatly accelerate the hybrid circuit design process.手机æ¿æ˜¯å…¸åž‹çš„æ··åˆç”µè·¯è®¾è®¡ï¼Œå¾ˆå¤šå¤§åž‹æ‰‹æœºè®¾è®¡åˆ¶é€ 商都利用Mentor åŠ å®‰æ°ä¼¦çš„eesoft 作为设计平å°ã€‚
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