FPGA quick start experience (part1)

There are many young people who have been separated from history, ruined the future, lost, confused and almost desperate. However, they are still young, youthful, creative, and struggling capital, many of which are not willing to be abandoned. The person covered. They are still working hard, hoping to take their future initiative more in their own hands. Learning and creating is a peaceful and successful road. But, what to learn, how to learn, how to use it, and where to use it?
There is a field, many people, especially young people who have studied microcontrollers are very interested. This is the development and application of FPGA chips, but in the face of the complicated technology involved in FPGA technology, everyone generally feels that it is difficult to learn, it is impossible to start There is no breakthrough, the prospect is unclear, lack of confidence, this post for the rapid introduction of FPGA or microcontroller, introduced a method: "Bai" 7-step FPGA quick start learning method for your reference.

The “Bai’s” learning method has two main purposes:

1. Let beginners get started quickly and easily
2. Discussing FPGA-related applications and market prospects with learners To achieve the first goal, we will use the “interspersed” learning skills. To achieve the second goal, we talk to learners about the industry’s commanding heights. ".

"Bai's" 7-step FPGA quick start learning method is divided into 7 parts

The first to fourth sections are “Plug-in” introductory learning, in order to allow beginners to quickly get started with knowledge, concepts and psychology in the shortest possible time. These four parts are applicable to both FPGA and microcontroller learning.
The fifth part to the seventh part are the introduction of the “sand-discussion”, telling the students the unique technical advantages, implementation skills and market prospects of FPGA.
These seven parts are:
Part 1: Understanding the download line and JTAG
Part II: Making the Easiest Development Board Part III: The Most Lazy Programming Part 4: Testing the Getting Started Results Part 5: SOPC and Implementation Skills Part 6: Professional Product Development Section 7: Personal Struggle - Specific IP Development
(Upper: Getting Started)
FPGA Getting Started Webinar: "Berner" 7-Step FPGA Quick Start Learning Method Part 1: Understanding Download Lines and JTAG
Many people find it difficult to learn FPGA or microcontroller, why? Too much content, too cluttered!
Our first step is to break down and simplify the problem. Whether it is the development of FPGA or single-chip microcomputer, it must involve three parts: development platform (computer), download line, development board (learning board)
among them
1. The development platform can be run in the early stages of development without the support of download lines and development boards.
2. The download line is only used when the target code is downloaded or debugged.
3. The development board can run independently after downloading. According to the above characteristics, we use various broken strategies to learn and analyze these parts.
The first is the simplest part of the download line.
Each manufacturer's development model is similar, there is a download line (some also claim to have debugging features), in appearance, these download lines are very similar, in fact, they use the same technology, are JTAG interface. The difference between the download lines of various manufacturers is mainly due to the difference in wiring position and order.
JTAG (Joint Test AcTIon Group)
It can be seen literally that this interface was originally a set of standards for the convenience of connection testing between circuit board chips, but is now widely used as a download line interface. Of course, the automatic self-testing design of electronic products will also be a very huge market, we will not discuss it here.
The download line generally uses a 10-core or 14-core cable and a corresponding plug (also has a 5-pin connector). In fact, in addition to the power and ground lines, JTAG has four valid signal lines: These four signal lines are: TCK , TMS, TDI and TDO, among them
TCK is a clock line that provides an operating beat signal for other signal lines.
TMS is a state control line that controls the state and state transition of the chip receiving or reading data.
TDI, you can input data into the chip according to the clock rhythm of TCK
TDO, when needed, reads data from the chip according to the clock rhythm of TCK. In the JTAG interface standard, TMS involves a concept of "state machine". Some students may understand that it is difficult at one time, do not force, skip first. As long as the trainee understands that when downloading or running debugging, the download line is the data channel between the development platform and the development board. It is enough to work under the control of the channel development platform. As for how to transmit the data and the specific content of the transmission, Take care of it. This is the characteristic of the so-called "interspersed" learning.
For the download line, you can understand, understand the download line, the relationship and interaction between the three parts of the development system will be clear. Not much, let's move on to the next step: start making development boards.

FPGA Introduction Learning Network Lecture: "Berner" 7-Step FPGA Quick Start Learning Method
Part II: Making the easiest development board

It’s not a joke to start making a development board yourself. To enable students to learn a method and grasp the "key points" of new technologies, FPGA chips and microcontroller chips are programmable single-chip systems. The operation or implementation functions of these chips require two basic conditions:
1. power supply
2. Loaded Code Powering the chip is a common problem for every electronic product. As for the download and operation of the target code control channel, both the FPGA and the MCU chip use the JTAG interface. To make the development board and let it work, it has to do two things. On the one hand, the signal lines of the JTAG interface of the chip. Connect to the corresponding signal line of the download line to establish a code download channel; on the other hand, provide the required power to the corresponding power supply pin of the chip. In principle, we only meet the most basic requirements of the development board.

Actually, we need to make a development board. There are three main links.

1. PCB board , empty board - now the chip is usually a chip package, you need a corresponding board to mount the chip. This experimental board can be used as a general-purpose test board that is commercially available, or it can be made by itself or by a training unit. During the training, students should be introduced to the main tool software and processing flow of PCB circuit board design and production.
2. Some portion of the power cord download single chip to chip may be powered. But for the students to learn, understand and master, we chose to use the three-terminal regulator block to power the chip on the development board. Regarding the design of the power supply, the separation of the analog power supply and the digital power supply, the grounding problem, the power consumption, and the like. It is the basis for the design of electronic products in the future. When training, students must master the design principles and essentials of power supply, because they may have few opportunities to learn this content. Due to space limitations, this post does not explain in detail.
3. The download and control channel sets a socket matched with the download line, and connects the four signal lines TCK, TMS, TDI, TDO of the chip JTAG interface with the corresponding signal lines of the download line, and at the same time, according to the need, the download line and the development board are Power and ground connection. After completing the above work, a simple development board is completed.
It should be noted that for the FPGA, the code is stored in RAM mode and will disappear after power failure. Therefore, in addition to the JTGA connection download, the target code of the FPGA can also be uploaded from the external memory chip to the FPGA chip after power-on. The FPGA chip is designed with a dedicated upload circuit.
In order to simplify the design, our development board adopts CPLD chip. The development method and main function of CPLD chip are the same as FPGA, but its function is simple (cannot embed CPU, etc.), but its target code can be stored in chip. Convenient and intuitive.
Although the "cottage" style development board is very simple, but in the content of learning, on the power supply, PCB, FPGA / CPLD similarities and differences and application focus, etc., teaching should not miss items. Remember, the "interspersed" we advocate is not to entangle non-critical issues, but it does not mean that they are completely ignored. All the knowledge can be gradually replenished.

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