The Delay Line has a wide range of applications in digital signal processing. For example, data delay lines are required in FIR filter design. In fact, data latency is required in most Pipeline designs. This paper introduces an implementation method based on EBR (Embedded Block RAM, Xilinx called BRAM, Altera called Embedded Memory).
As shown below:
The EBR is configured as a single port RAM (ie RAM_DQ), where the Write Mode is configured as Read before write. That is, when the same address is read and written at the same time, the original data of the changed address space is first read, and then new data is written into the address space. As shown below:
The waveforms in this mode are:
Assuming the counter mode is 4 and the WE signal is tied high, the initial value of RAM is 0, then the corresponding timing diagram is shown below:
In the first frame address, the data read from the address 0 is 0, and the data A is written into the address 0, the data read from the address 1 is 0, and the data B is written to the address 1. Similarly, data C and data D are written to addresses 2 and 3, respectively. In the second frame address, the data read from address 0 is the data A written in the first frame address. Similarly, the data read from addresses 1 to 3 are B, C and D. Since we have enabled the output registers, there is a total of 5 cycles of Latency from the input DIN to the output DOUT.
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