As mobile internet equipment becomes more and more popular, more and more manufacturers compete to design the latest and most fashionable products. Low power consumption is always the biggest concern of handheld devices, which includes the power consumption of their display components. According to the survey results of market research company iSuppli, the processors provided by Intel for these devices occupy half of the market. To replace the traditional, outdated RGB parallel bus, Intel used the LVDS and MIPI DSI bus interfaces in the recently released Moorestown processor.
MIPI DSI is the latest display standard for mobile handheld devices. By configuring a scalable data channel, this interface can achieve a data transmission rate of 3Gb / s, which uses low-voltage swing differential signals and has a very low output signal level. ECC and CRC checksums are also embedded in the data message to allow the receiver to perform error correction and recovery.
Application is developing
In the past few years, as MIPI DSI and DCS standards matured, display manufacturers began to follow these standards in their products. Due to the complexity of mixed-signal design and the uncertainty of rising market demand, mobile Internet equipment manufacturers can only obtain a few displays with integrated MIPI interfaces. Initially, most display manufacturers preferred the new and old standard bridging solution before producing displays with integrated MIPI functions. This can convert the high-speed serial interface to the traditional parallel RGB interface to test the market response.
As shown in Figure 1, MIPI supports the following two display standards.
Figure 1 (a) MIPI video mode working block diagram (b) MIPI DCS command mode block diagram
1 DSI video mode
This working mode is similar to the traditional RGB interface, the host needs to continuously refresh the display. Since no dedicated data signal is used to transmit synchronization information, control signals and RGB data are transmitted in the form of messages through the MIPI bus. Because the host needs to refresh the display regularly, the display does not need a frame buffer.
2 DCS command mode
The MIPI bus controller uses display command messages to send pixel data streams to the display. The display should have a full frame buffer to store all pixel data. Once the data is placed in the frame buffer of the display, the timing controller takes the data from the frame buffer and automatically displays them on the screen. The MIPI bus controller does not need to refresh the display regularly.
The advantages and disadvantages of the two modes
In terms of cost and power consumption, each operating mode has advantages and disadvantages. The video mode display architecture does not require a frame buffer. However, the host periodically consumes a large amount of average energy by sending DSI video messages in high-speed mode.
Ideally, when the display content does not change (or does not change often), the central processor of the display system should switch to a low-power mode, and the link between the processor and the display will be activated when needed. Due to the need for the host to refresh regularly, some central processors and memory interfaces also need to remain active, which can prevent the system from reaching the best power budget.
On the other hand, the command mode display architecture allows the display to self-refresh the entire frame buffer directly. However, it is always costly to integrate a full-frame long frame buffer in the display, especially the high-resolution display required by most users today. This requires the interface chip to have a larger die size. Display manufacturers also have to provide display controllers with a specific capacity frame buffer for each display resolution.
For video mode and command mode display architectures, it is usually necessary to program the register of the display controller to set the corresponding display resolution, aspect ratio and working mode. MIPI does not define any standard protocol to access these internal registers, so different display manufacturers can customize their own dedicated command set.
In order to get rid of the conflict between the display commands of different manufacturers, some manufacturers prefer to allow the display to initialize itself, so that the display can work normally without the configuration of the MIPI host controller. In this case, the display usually has a PROM memory that stores display parameters. This is very convenient, but PROM also occupies a relatively large memory space.
Design considerations
In order to achieve the best system utilization, equipment manufacturers also need to consider the following factors.
â— An LDO power converter with high conversion efficiency should be integrated inside the display, and only one external power supply voltage should be input to the display system.
â— For the clock generated by the internal PLL, an external input reference clock is usually required. The frequency of the reference clock ranges from 32kHz to several megahertz. D-PHY is a scalable, low-power, high-speed physical layer standard that several MIPI interface standards will support. Some D-PHY timing parameters also require a reference clock as a signal reference. Combined with the use of reference clocks, frequencies in the range of a few ten megahertz are commonly used. Usually, an internal oscillator will generate a very low frequency clock as the reference clock and feed it back to the PLL, and multiply the frequency to generate the frequency required by the display controller D-PHY logic.
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