Verilog and SystemVerilog define four description signal states: 1, 0, X, and Z. 1 and 0 are undoubtedly true signal states. Z is used to indicate high impedance and X is used to indicate indeterminate states.
The X signal can be created intentionally or unintentionally. The most common X signal exists in the uninitialized memory register, where X is used to indicate the unknown state of these memories before reset. Other scenes that can produce X include different drivers driving the same block of logic to different logical values, either a shutdown signal in low power or a multi-bit signal that exceeds the selected range. Some designers set the signal for those dont care in design to X, allowing the synthesis tool to randomly select 0 or 1 for optimization when optimizing. Some designers also set X for the logic values ​​that will not be used in the design for the purpose of debugging. If you use these logics during simulation, it means that the circuit has a problem, and the X generated by the simulation tool can check these. logic. Deliberately setting some X signals is a more controversial practice. It will also be identified when doing a lint check. However, some X states can produce erroneous simulation results due to simulator recognition (verilog X optimism). This is a bug in RTl.
The first example of verilog X optimism comes from the if...else statement:
| 1 2 3 4 5 6 | Always_ff@(posedge clk)begin If(cond) c <= a; Else c <= b; End |
Verilog LRM indicates that if the condition of if...else is the X state, then this condition will be treated as false, where only the else statement will be executed.
There is a situation in the actual design that may cause this problem: the cond signal comes from memory. For example, the SEDDED (single error correction double error detection) decoder detects a sequence of registers that store Hamming codes. Whether the cond of this sequence is incorrect is generated by a combination of these registers, and output error when cond is TRUE. Signal error=1. Before the reset, these registers are in the X state. The original error signal should be error=1, but in the simulation, due to the feature of verilog X optimism, the X of the register is propagated to the cond by the combinatorial logic, and finally the cond=X is judged as FALSE. The output error signal is 0, which is contrary to the actual circuit behavior.
Another example of Verilog X optimism is the case statement:
| 1 2 3 4 5 6 | Always_ff@(posedge clk)begin Case(cond) 1'b0 : c = a; 1'b1 : c = b; Endcase End |
In the case statement, if cond is X, c will retain the original value. This originally describes the behavior of a mux, but due to X optimism, the simulation behavior is inconsistent with the RTL description.
In addition, Verilog X optimism also affects the processing of 0/1->X/Z. The following state transitions are treated as posedge:
0->1, 0->X, 0->Z, X->1, Z->1
0->X or X->1 is not necessarily a posedge, but in the simulation, they are treated as posedge.
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